Any of you ece fellas know how I might prove (theoretically) that this circuit is stable?
From my testing, it is stable. But there are a couple conditions that I'm a bit displeased with (like current limit near 0V causes a little impulse which ripples to the output).
I would just say this is good enough, but it's for my project 'portfolio' and I wanted to "prove" that it will be stable. I've analysed the voltage control stage and the bode plot looks great, but I'm not sure how I would ensure that the V->I limit transition, and the current limit itself will be stable.
I figured I could DC bias the circuit to run in current limiting, and check the bode plot that way, but that transition point I have no idea. Maybe add some hysteresis and call it day?
From my testing, it is stable. But there are a couple conditions that I'm a bit displeased with (like current limit near 0V causes a little impulse which ripples to the output).
I would just say this is good enough, but it's for my project 'portfolio' and I wanted to "prove" that it will be stable. I've analysed the voltage control stage and the bode plot looks great, but I'm not sure how I would ensure that the V->I limit transition, and the current limit itself will be stable.
I figured I could DC bias the circuit to run in current limiting, and check the bode plot that way, but that transition point I have no idea. Maybe add some hysteresis and call it day?
